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Not only, I think, bottom-up consumption, but also top-down. So, in general, of course, would be very useful. Yeah, yeah, yeah, yeah. That's an important input that could be given. Okay. And I can add then, as you understood, in fact, from talent funds, we didn't propose anything to you because we consider that our need is not the most demanding one. So, that's why we share your assumption that the important input is fund value. Yeah, the fund is good. Okay, thank you. Marco, from Monaco, we have some experience out of kids. Okay. So, I would say... So, you don't have layers visible in the layout view? No, we don't. I mean, usually, one should see, I guess, to the left in this virtual, so you should have the library visible, but it doesn't appear for us visible yet. So, the technology library is not visible? No. You know why? I do. The path to that library should be in your cds.lib file. Okay. And if it's not visible, if it is, then it should be visible. Then it might be that when you open the layout, the layers are not visible. If that happens, you are missing the display.tr file. Okay. Yeah, okay. Thank you. I'm trying to remember what you said there about... Could you maybe just, if I may, send a short e-mail? Just explaining? Yeah, I guess I can. Okay, thank you. Thank you very much. Okay, thank you, Marco. That's wonderful. Thank you, my Swedish colleague. So, maybe, before you can confirm the progress from NSERC, today you targeted subcontractors and there is a schedule issue with that, isn't it? Okay, so, a few things. Yes, so, our effort started, but our effort primarily now is accreditating the subcontractors. I think this has to be done by the European Union such that the ownership is only... I have to state what the ownership is. It's not like that. They already have a rough view what then to design, but this is, in principle, the effort. That's also speaking of the schedule. I mean, probably because we target an NPW later next year because we have to kind of stick to the set, to ISP in that case, and I think there is a September, October NPW that we want to apply to CHIP. So, we probably have to extend that working time year to schedule that. I think I missed that in Roland's excerpt because we have to extend it in order to get the hardware agents to measure it. So, I mean, there will be some kind of dead time anyway when we wait for the CHIP. We have to stick to that, but yes. But, in principle, it doesn't really contradict to the time schedule of the hardware work package. It just means that, in principle, we get the results kind of by the end. Proven by it, if we do hardware, we have at least four to six months of the various applications. But, yes, so this is our effort. So, we have also in parallel, I mean, giving it to the subcontractor, doesn't mean that we do nothing ourselves. We have set up the PDK. We can simulate. We also did, let's say, some simulation stuff, also not strictly related at all, but we set up the design environment also to support the subcontractor. We also talked about the specifications, which are still more or less bottom-up, what to achieve. And, I mean, this was a kind of effort starting designing without clear specifications. So, this is a little bit what we all do. So, this is our part. Maybe just one thing that I just realized is that I changed what Roland sent you last time. And, that's why I was also a bit struggling, because we, in that proposal, we combined all the effort into the RSVG and chip that we sent. We didn't really split that up. So, maybe there's kind of a misunderstanding, or maybe we have to maybe discuss that again with Roland. It might have been a little bit different way how he wrote and also had in the X machine. There, he combined the effort of the RF chain design in the chip that he sent. Explicitly what I meant, because for us, these topics come along with the chip that he sent. And, I think, if I look at the purpose for him, it's also the same. We do not really split that up if we do primarily chip that he sent. So, I don't know. It's now a little bit different for me than what Roland sent by the end of September back then. Maybe we have to discuss that again. Okay. In fact, if I understand well, you... The impact is mainly for the report. And, if you say, for process engineering, for chiplets, or work on the RF chain design is really related to the chiplets we target, we want to report those activities in a single entire document for the deliverable. And, for you, it might be easier than to get the entire document for the work activities you get for the chiplets. Is it a good understanding? Yeah, I think so. I mean, because we didn't really have the explicit RF chain design in mind So, this part will be covered in by the end of the chiplet design. That is probably... But also, again, if I check the other... I think also if you do pure chiplet design, you have to do some kind of RF chain design. But in the chiplet design, it's nothing that you more or less do so much separately. It's a registered process. Yeah, okay. Understood. So, please speak to us and confirm your position by email so that we can take it to account. I think those fit, of course. But, please... Yeah, I can do that. Please also take it to account that some of your assumptions that you take for your chiplets could be also useful for other partners. Yeah, right. And can you distribute... I guess you distribute the slides because then we can compare what we had in mind and now I think what you proposed. Yeah. Okay. I will do that. When I have the slides, I will discuss what I'm going to do and come back to you. Okay. Okay, perfect. Okay, so... Maybe Peter... So, this time it's Peter Bianchi. Is there more to what you know? Yes. What I said... I think it's 5 minutes in. We started the design of the down-converter chiplet in global family technology and then by CMOS process. We are currently reconsidering CMOS, pure CMOS, to be better. We will decide soon between one of the two. For the other two chiplets, I think we will start them before the end of this year. Probably next month. Also, both also in global family technologies, probably. Okay. Great, yeah. At the end, we will implement on the one, see if there are other ways. We will prototype on the one. That's why... No, prototype... No, we prototype... No, no... Design is all paper. It's critical. I hope it's critical. Yes. Okay, okay. Hang on, hang on, hang on. Sorry, I'm sorry. I'm in a confusion. Sorry. Okay, okay. Perfect. Okay. So, thank you for the news. What about Mapple and Jerry? And the one chiplet... I'll check. I'll check. It was... Michael going to say something. But... Well... If I start from what I know, so that... Don't worry. Sorry. AT&T, chiplet design is only given to FDX. And my understanding was that it will be they don't during the summer time of 25. And... On the status side, basically, there will be like three parts. Input buffer, and then the AT&T core. So, ESP for the sub-AT&T. And my understanding is that basically, system modeling is pretty much done. And even some sub-lock layouts have been drawn. So, Michael wants to add something. Yeah, I can elaborate a bit. Can you hear me? Yeah, so the modeling part is we have the full simulation chain for the system that we are doing. It's a down-converting ADC in which we have merged the analog FYI to the sampling of the ADC. And we have simulation model for that so that we can have a lot easier to simulate the performance metrics of the system. And we have started to do the designs. And, as I said, we have some sub-works already. The one aspect that we are studying is how we can use programmatic means to generate those sub-works. So, I'll be working, for example, on bootstrap sampling switch generator and mixer switch generator and some supporting logic or supporting building blocks for the sub-AT&T and so forth. The design is ongoing. It has started, but it's not ready yet. And for the DSQ side, we think that we are going to add a minimal supporting digital part that will be controlled by ARISC by microprocessors so that we can programmatically extract the measured data from the receiver channel. So, this is the current plan for the implementation. Okay. So, I understand that you are in line and there is no issue to be taken into account and you enjoy your design activity. Yes, that's correct. Everything is going as planned. Okay. Perfect. Okay. Thank you. Maybe we can switch to the CD one by one. Yes. Can you hear me? Perfect. Yes. Like I said in the previous meeting, we are already for the case. Finally, we will be directing in the C4 technology, but we are waiting for my partner, Mario, who is in charge of the design, to be granted the permission to accept the PDK. So, we are estimating that maybe next month, we will be starting the design and by the end of 2045, we will be making a debut. So, yes. That's what we have right now. Okay. So, everything is also online. Maybe you are a little bit late, but on the end of 2045, it's actually late, I'm sorry. And so, I assume that you started with ADC and the DAC will come very soon. Is that right? Yes, exactly. The ADC has just started the refining and the DAC is starting probably next month. And at the end of 2045, we will be making the debut. We have some specifications already. Okay. And you are still in the position to say, today, we do not prototype. But we do not identify yet an opportunity to prototype. Is that right? Is that the same position? Sorry? Could you repeat? I mean, you don't want to include the prototype in the scope. Is that right? Or is it part of the scope? No, no, sir. We are making the debut in parallel with the project. If it is feasible to rely on for the specification, it will be... we will make it. But I don't know if the debut will take longer or... But you are right. The specifications that we are providing to you are going to be from the design not for the take-out, probably. Yes, that's the question. You may answer later on, when you will have a better view on the opportunity to include it in our toolbox. OK. OK. OK. Thank you. So, that's it. Maybe someone from the University of Padua. Is there somebody from the University of Padua? I cannot see. OK. So, we can go finally to the statements. Bruno or Nicolas, any news about your design progress? Yes. So, we have already started on the architecture work and the design of the RFJAC. Nicolas is in charge of the design. So, currently, we are pushing the design that we have done in 2020. From 7 seconds to 15, so double the rate. And we will produce also the RF module to further expand the output frequency as it will be designed in the architecture. So, we are exploring the possibility to use KMOS transistor. We have KMOS transistor for the switching core of the DAC. And we are working also on the data path. So, the chain that will supply the data to the switching core to optimize for the required speed. So, we have already the semantics for the complete DAC. And we are optimizing the different to optimize the to meet the best performance for the speed that we are considering. Ok. Just an additional question. You are in that phase of optimization already. Is there any additional input, refined input for that optimization? No, no. The optimization for the speed. So, the speed is clear. But when it comes to the noise, to the linearity, maybe further input if we cannot achieve what we have targeted. But so far, we are not yet there. So, we are working on the speed that we want to meet. Ok. Thank you. Thank you for those news. So, we have finished the list of sub-tasks. Are there any other information that you want to share? Other suggestions? So, ok. If there are other subjects, I will send you, as it was requested, the slides with action for some partners. Those actions are mainly related to the work and organization. So, an action for employment and to meet and also to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet and to meet